Phase noise reduction in voltage controlled oscillators

ABSTRACT

A voltage controlled oscillator (VCO), a method of designing a voltage controlled oscillator, and a design structure comprising a semiconductor substrate including a voltage controlled oscillator are disclosed. In one embodiment, the VCO comprises an LC tank circuit for generating an oscillator output at an oscillator frequency, and an oscillator core including cross-coupled semiconductor devices to provide feedback to the tank circuit. The VCO further comprises a supply node, a tail node, and a noise by-pass circuit connected to the supply and tail nodes, in parallel with the tank circuit and the oscillator core. The by-pass circuit forms a low-impedance path at a frequency approximately twice the oscillator frequency to at least partially immunize the oscillator core from external noise and to reduce noise contribution from the cross-coupled semiconductor devices.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation of copending U.S. patent applicationSer. No. 15/093,194, filed Apr. 7, 2016, which is a continuation of U.S.patent application Ser. No. 14/152,330, filed Jan. 14, 2014. The entirecontents and disclosures of U.S. patent application Ser. Nos. 15/093,194and 14/152,330 are hereby incorporated herein by reference in itsentireties.

STATEMENT OF GOVERNMENT INTEREST

This invention was made with Government support under Contract No.:FA8650-09-C-7924 (Defense Advanced Research Projects Agency (DARPA)).The Government has certain rights in this invention.

BACKGROUND

This invention generally relates to voltage controlled oscillators, andmore specifically, to reducing noise in such oscillators.

In general, a VCO (voltage controlled oscillator) is an oscillatorcircuit that outputs an AC signal having a frequency that varies inresponse to an input control voltage. VCOs are fundamental componentsthat are employed in a broad range of applications including radar andcommunications systems (e.g., wireline or wireless applications) fordata transfer and recovery processes. By way of example, VCOs areutilized for PLL (phase locked loop) circuits, DLL (delay locked loop)circuits, and injection locked oscillators. VCOs are further employedfor applications such as frequency translation, data modulation, clockdistribution and clock/data recovery.

In the operation of a VCO, an undesired random phase component, referredto as phase noise, is often introduced into the oscillator output. Thisphase noise, which varies over time, may be due to the thermal noisepresent in the components of the oscillator, loss in the passivecomponents, and to other factors. Oscillator phase noise is a keyperformance metric in many oscillator applications including manywireless and wireline communications applications, radars, sensors,images, data converters, and so forth.

BRIEF SUMMARY

Embodiments of the invention provide a voltage controlled oscillator(VCO), a method of designing a voltage controlled oscillator, and adesign structure comprising a semiconductor substrate including avoltage controlled oscillator.

In one embodiment, the VCO comprises an LC tank circuit for generatingan oscillator output signal at an oscillator frequency (f_(o)), and anoscillator core including first and second cross-coupled semiconductordevices connected to the tank circuit to provide regenerative feedbackto the tank circuit to help maintain the oscillator output stable. TheVCO further comprises a supply node connected to the tank circuit and tothe oscillator core for connecting the VCO to a voltage source, a tailnode connected to the tank circuit and to the oscillator core forconnecting the VCO to a current source, and a noise by-pass circuit. Thenoise by-pass circuit is connected to the supply node and to the tailnode, in parallel with the LC tank circuit and the oscillator core, andforms a low-impedance path at a frequency approximately twice theoscillator frequency to at least partially immunize the oscillator corefrom external noise and to reduce noise contribution from thecross-coupled semiconductor devices.

In one embodiment of the voltage controlled oscillator, the noiseby-pass circuit comprises a series resonance tuned to resonate atapproximately twice the oscillator frequency.

In one embodiment of the voltage controlled oscillator, the noiseby-pass circuit includes a capacitor and an inductor located in series.

In one embodiment, of the voltage controlled oscillator, the noiseby-pass circuit includes a capacitor and a transmission line located inseries.

In one embodiment, the voltage controlled oscillator further comprises afrequency control to apply a variable signal to the noise by-passcircuit to adjust the frequency at which the noise by-pass circuitresonates.

In one embodiment, the frequency control includes a variable voltagesource to apply a variable voltage to the by-pass circuit to adjust thefrequency at which the noise by-pass circuit resonates.

In an embodiment, the frequency control includes a variable digitalsignal source to apply a variable digital signed to the by-pass circuitto adjust the frequency at which the noise by-pass circuit resonates.

In an embodiment, the noise by-pass circuit includes a variablecapacitor, and the frequency control applies the variable signal to thevariable capacitor to vary a capacitance thereof and thereby to vary thefrequency at which the noise by-pass circuit resonates.

In an embodiment, the noise by-pass circuit includes a capacitor and atransmission line, and the frequency control applies the variable signalto the transmission line to vary the frequency at which the noiseby-pass circuit resonates.

In one embodiment, the noise by-pass circuit includes a capacitor.

In one embodiment, the invention provides a method of designing avoltage controlled oscillator comprising an LC tank circuit forgenerating an oscillator output, an oscillator core to provideregenerative feedback to the tank circuit, supply and tail nodes, and anoise by-pass circuit. The method comprises designing the oscillatorcore to generate the oscillator output at a frequency of f_(o), biasingthe core, and connecting the core to a voltage supply; designing thenoise by-pass circuit at approximately twice the frequency of theoscillator output; and introducing the noise by-pass circuit into theVCO. The noise by-pass circuit is connected to the supply node and tothe tail node, in parallel with the LC tank circuit and the oscillatorcore, to at least partially immunize the oscillator core from externalnoise and to reduce noise contribution from the oscillator core. Themethod further comprises tuning the noise by-pass circuit to obtain aspecified performance of the VCO.

In one embodiment, the noise by-pass circuit is designed to include acapacitor and a transmission line in series.

In an embodiment, the capacitor and the transmission line in the noiseby-pass are selected so that the noise by-pass circuit resonates atapproximately twice the frequency of the oscillator output.

In an embodiment, the noise by-pass circuit is connected to a variablesignal to vary the frequency at which the noise by-pass circuitresonates.

In one embodiment, the noise by-pass circuit is tuned by adjusting thevariable signal connected to the noise by-pass circuit to adjust thefrequency at which the noise by-pass circuit resonates to obtain thespecified performance.

In one embodiment, the invention provides a design structure tangiblyembodied in a machine readable medium for design, manufacturing, ortesting a semiconductor device. The design structure comprises asemiconductor substrate including a voltage controlled oscillator(VCO.). The VCO comprises an LC tank circuit for generating anoscillator output signal at an oscillator frequency (f_(o)), and anoscillator core including first and second cross-coupled semiconductordevices connected to the tank circuit to provide regenerative feedbackto the tank circuit to help maintain the oscillator output stable. TheVCO further comprises a supply node connected to the tank circuit and tothe oscillator core for connecting the VCO to a voltage source, a tailnode connected to the tank circuit and to the oscillator core forconnecting the VCO to a current source, and a noise by-pass circuit. Thenoise by-pass circuit is connected to the supply node and to the tailnode, in parallel with the LC tank circuit and the oscillator core, andforms a low-impedance path at a frequency approximately twice theoscillator frequency to at least partially immunize the oscillator corefrom external noise and to reduce noise contribution from thecross-coupled semiconductor devices.

In one embodiment, the noise by-pass circuit comprises a seriesresonances tuned to resonate at approximately twice the oscillatorfrequency.

In an embodiment, the noise by-pass circuit includes a capacitor and aninductor located in series.

In an embodiment, the noise by-pass circuit includes a capacitor and atransmission line located in series.

In an embodiment, the VCO further comprises a frequency control to applythe variable signal to the by-pass circuit to adjust the frequency atwhich the noise by-pass circuit resonates.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 shows a conventional VCO architecture.

FIG. 2 illustrates a prior art technique for reducing tail noise in thearchitecture of FIG. 1.

FIG. 3 depicts a second prior art technique for reducing tail noise inthe architecture of FIG. 1.

FIG. 4 illustrates another technique to reduce tail noise in thearchitecture of FIG. 1.

FIG. 5 shows a VCO architecture in accordance with an embodiment of thisinvention.

FIG. 6 illustrates an alternate embodiment of this invention.

FIG. 7 depicts a third embodiment of this invention.

FIG. 8 shows a control option that may be used in an embodiment of thisinvention.

FIG. 9 shows a second control option that may be used in an embodimentof this invention.

FIG. 10 illustrates a third control option that may be used in anembodiment of this invention.

FIG. 11 shows a further embodiment of the invention.

FIG. 12 illustrates an embodiment of the invention that also includes anintegrated differential doubler.

FIG. 13 illustrates a procedure for designing a VCO according to anembodiment of the invention.

FIG. 14 schematically illustrates an embodiment of the inventionimplemented in an integrated circuit.

FIG. 15 shows a block diagram of an exemplary design flow that may beused in embodiments of the invention.

DETAILED DESCRIPTION

FIG. 1 illustrates a voltage controlled oscillator (VCO) 100. VCOcomprises a tank circuit 102 and an oscillator core 104. Tank circuit102 includes inductor 106 and capacitor 110, and the oscillator core 104includes a pair of cross-coupled transistors 112,114. At one end of theoscillator, inductor 106 is connected to a reference or supply voltageV_(dd), and the other end of the oscillator is connected to a currentsource 116 and to ground.

VCO 100 comprises an LC VCO topology based on the parallel resonance ofinductor L 106 and capacitor C 110 of tank circuit 102. The tank circuitoscillates at its resonant or natural frequency (f₀, where ω_(o)²=1/LC), determined by the tank circuit capacitance and inductance. Anideal tank circuit (just L and C) will oscillate purely sinusoidally atits natural frequency, indefinitely. Since nothing is ideal, all tankcircuits include resistance (R). Inductor current lags voltage andcapacitor current leads voltage by ninety degrees (90°). Thus, becauseresistor current is in phase with voltage across the resistor, tankcircuit resistance shifts the phase (Δω) in the tank circuit, dampensthe tank circuit oscillation, and determines what is known as the tankcircuit's Q factor or Q.

Therefore, typical state of the art oscillators require regenerativefeedback to maintain oscillation. Phase noise is a measure of signalspread (and Q) and satisfies

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w, where k is the Boltzman constant, T is the operating or ambienttemperature, V_(RMS) is the root mean square of the tank circuitvoltage, and

$F = {1 + \left( \frac{4\; \gamma \; {IR}}{V_{0}\pi} \right) + {\frac{8\; \gamma \; g_{mbias}R}{9}.}}$

Also, for communications, phase noise is a critical parameter formeasuring data transfer quality and reliability.

Essentially, Q indicates tank circuit efficiency, peak energy stored inthe tank circuit (reactance,

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with respect to the average energy dissipated (in the tank circuitresistance R) at resonance, i.e., Q=L/RC. Low Q circuits are, therefore,lossy and more heavily damped. Thus, the higher the Q, the closer toideal the local oscillator tank circuit. All oscillators have someinherent/parasitic resistance, e.g., from wiring, contacts and drivers,that lowers the tank circuit Q. Minimizing this inherent/parasitic tankcircuit resistance and parasitic capacitance is a focus of oscillatordesign, as is otherwise compensating for any residual resistance andparasitic capacitance.

To offset inherent, parasitic resistance, a typical oscillator includesa pair of cross coupled devices (e.g., bipolar transistors, field effecttransistors (FETs) or logic gates, such as inverters) connected to an LCtank circuit. The cross coupled devices add negative resistance as theLC oscillates, thereby providing regenerative feedback. However, thecross coupled devices may also add more resistance and/or morecapacitance (which shifts the resonant frequency). Further, circuitcomponent age and ambient conditions, e.g., operating voltage andtemperature, can alter the characteristics of the oscillator to shiftthe resonant frequency away from nominal. A typical voltage controlledoscillator is a tunable oscillator where a control voltage is adjustedto shift the VCO operating frequency, for example, to re-center thefrequency and/or compensate for phase shift. For the state of the artvoltage controlled oscillator, either the LC tank still drives outputbuffers directly or the LC capacitively drives the output buffersthrough a tapped capacitance network.

With the design 120 of FIG. 2, a transistor 122 is located in seriesbetween the oscillator circuit 100 and ground, and current source 117 isconnected to the VCO via the diode-connected transistor 124. Vdd isconnected to one end of the current supply, and the second end of thecurrent supply is connected to transistor 124. Transistor 124 isconnected to ground, and the gate of transistor 122 is connected to thegate of transistor 124. Note that the combination of transistors 124 and122 is only one of many ways to implement current biasing to the VCO(i.e. a transistor implementation of the current source 116 in FIG. 1)and those skilled in the art will know multiple other implementations.The phase noise reduction techniques which are the subject of thisdisclosure are applicable regardless of the specific way to implementcurrent biasing at the source of 112 and 114.

A number of techniques are used to reduce the phase noise in a VCO, andFIGS. 3 and 4 illustrate two prior art oscillators where techniques areapplied to reduce phase noise.

The arrangement of FIG. 3 reduces noise, referred to as tail noise, fromthe tail node of the VCO. As one example:

-   -   Simulated phase noise for a 37 GHz oscillator: −121.5 dBc/Hz;    -   Contribution from tail source thermal noise: 2.6×10⁻¹³ V²/Hz @        25 MHz offset;    -   Tail noise at 2f_(osc) gets downconverted to output phase noise        at f_(osc).

With the design 140 of FIG. 3, a capacitor 142 is added in parallel withthe current source 116. This technique reduces tail noise by shortingout that noise. A very large capacitor is needed to short out the noisesufficiently.

FIG. 4 illustrates a VCO 160 employing the phase noise reductiontechnique of FIG. 3. This circuit 160 also includes an RF choke 162between inductor 106 and V_(dd). Note that an RF choke can beimplemented by a transmission line, an inductor or a combination ofother circuit elements which are known in the art. In the example ofFIG. 4, capacitor 164 has a capacitance of 45 pF using vncaps (B3−M1)and uses a 100 um×100 um area. With this circuit:

-   -   Simulated phase noise for a 37 GHz oscillator: −122.5 dBc/Hz;    -   Contribution from tail source thermal noise: 1.9×10⁻¹³ V²/Hz @        25 MHz offset: 27% lower noise from tail source.

FIG. 5 shows a VCO 200 incorporating a noise reduction technique 202 inaccordance with an embodiment of this invention. The architecture ofFIG. 5 includes a capacitor 204 connected in parallel with tank 102 andcross-coupled transistors 112,114. This design also includes an RF-chokeT₁ connected between inductor L 106 and V_(dd).

With the design of FIG. 5, the tail noise and the supply noise by-passthe tank 102 and the cross-coupled transistors 112, 114 of the VCO. Inan embodiment of the invention, the capacitance of capacitor 204 isrelatively large, and as an example, C 204 may have a capacitance of 10nF.

As an example:

-   -   Simulated phase noise for a 37 GHz oscillator: −126.6 dBc/Hz;    -   Contribution from tail source thermal noise: 0.48×10⁻¹³ V²/Hz @        25 MHz offset: 82% lower noise from tail source.

The design of FIG. 5 provides better performance than the tailcapacitance short of FIG. 4 because with the design of FIG. 5, the noisefrom T1 206 also by-passes tank 102 and cross-coupled transistors112,114. In a simulation, the circuit of FIG. 5 also reduced noise fromthe cross-coupled transistor pair.

FIG. 6 shows an alternate embodiment 220 of this invention, in which aninductor 222 is added in series with capacitor 224. The inductor 222 andcapacitor 224 are tuned to resonate at twice the frequency of theoscillator (2f_(osc)), forming a low-impedance path at that frequency.Because the impedance seen towards this noise bypass circuit (formed byinductor 222 and 224) is lower than that seen towards the VCO core, thenoise from the tail current source at 2f_(osc) that flows into the VCOis reduced significantly. In embodiments of the invention, the design ofFIG. 6, in comparison with the design of FIG. 5, uses smallercomponents. For instance, in the architecture of FIG. 6, a 100 pH t-lineand a 250 fF capacitor 224 may be used. As an example: Simulated phasenoise for 37 GHz oscillator: −126.6 dBc/Hz (as good as C 204 of FIG. 5)

In a simulation, the circuit of FIG. 6 also reduced noise from thecross-coupled transistor pair; and in some cases, the short at 2f_(osc),of FIG. 6, performs slightly better than the circuit of FIG. 5.

FIG. 7 depicts a third embodiment 240 of the invention. In this design,a transmission line T2 242 is used instead of an inductor. Line T2 andcapacitor 244 are tuned to resonate at twice the frequency of theoscillator (2f_(osc)). The t-line 242 may be simpler to implement in aphysical design than the inductor 222 of FIG. 6, and the t-line does notcouple strongly with the tank inductor.

In embodiments of the invention, the frequency of the noise by-passcircuit can be changed. For a voltage controlled oscillator where thefrequency of oscillation can be altered using a control voltage, anothercontrol voltage can change the frequency of the bypass circuitappropriately. The frequency of resonance of the bypass circuit can bechanged, for example, using a variable capacitor (varactor), or avariable transmission line/inductor or both. The tuning of the frequencyof resonance of the by-pass circuit can also be used to trade-offbetween noise from the gm-cell and noise from the tail bias circuit whenthe VCO is oscillating at a particular frequency. This trade-off can beused as a phase noise optimization for manual or digital-basedcalibration of the oscillator.

FIGS. 8, 9 and 10 show three controls that may be used in embodiments ofthe invention.

With the embodiment 300 of FIG. 8, capacitor 302 is a variablecapacitor. A first voltage control V₁ 304 is shown applied to capacitor110, and second voltage control V₂ 306 is applied to capacitor 302. Thevoltage control V₂ is used to control the capacitor 302 such that T₂ 310and the capacitor resonate at approximately 2f_(osc), with adjustmentsthereto to improve or optimize the overall performance of theoscillator.

With the arrangement 320 shown in FIG. 9, digital control set O₂ 322 isapplied to transmission line T₂ 324. The control is used to set theinductance of the transmission line so that T₂ and capacitor 326resonate at approximately 2f_(osc), with adjustments thereto to improveor optimize the overall performance of the oscillator. With thisembodiment, as illustrated in FIG. 9, capacitor 326 does not need to bea variable capacitor.

The circuit 340 of FIG. 10 includes both a variable capacitor 342 and avariable inductance transmission line T₂ 344. Voltage control V₂ 346 isapplied to capacitor 342, and digital control set O₃ 350 is applied totransmission line T₂. The two controls V₂ and O₃ may be used in tandemto adjust the frequency of the by-pass circuit to adjust or optimize theperformance of the oscillator.

In embodiments of the invention, V₁, V₂ and O₃ may be linearly relatedto each other and can be set using an analog or a digital based control.

The by-pass technique of embodiments of the invention can be extended toa fully decoupled oscillator, as well as to other VCO architectures thatutilize a core LC oscillator circuit separated from supply and groundthrough biasing circuits or interconnects.

For instance, FIG. 11 shows a fully decoupled, LC tank based oscillatortopology in accordance with an embodiment of this invention. The LC tankbased oscillator topology 400 includes an inductor 411, a capacitor C421, a capacitor C 422, a capacitor C_(c) 425, a capacitor C_(c) 426, anactive device 431, an active device 432, an LC tank 440, and a currentsource 444 implemented in this case by an FET device.

The gate (or base) of active device 431 is connected to a side ofcapacitor C_(c) 426 and a side of LC tank 440. The gate (or base) ofactive device 432 is connected to a side of capacitor C_(c) 425 and aside of LC tank 440. Another side of capacitor C_(c) 426 is connected tothe drain (or collector) of active device 432, a side of capacitor C 422and inductor 411. Another side of capacitor C_(c) 425 is connected tothe drain (or collector) of active device 431, a side of capacitor C_(d)421, and a side of inductor 411. Another side of capacitor C_(d) 421 isconnected to another side of capacitor C_(d) 422. Inductor 411 isconnected to a voltage V_(DD). Sources (or emitters) of active devices431 and 432 are connected to each other and to a tail node 444.

In the example of FIG. 11, the active devices 431 and 432 are(n-channel) MOSFETS. However, given the teachings provided herein, it isto be appreciated that one of ordinary skill in the art can readilyimplement the topology 400 of FIG. 11 with respect to other types ofactive devices. Moreover, the same type of device may be used, e.g., aMOSFET, but using a p-channel version. These and other variations in thecircuit elements of topology 400 are readily determined and implementedby one of ordinary skill in the art given the teachings provided herein.

VCO design 400 includes a noise by-pass circuit 450 comprised of avariable capacitor 452 and transmission line T₂ 454. One end of circuit450 is connected to V_(dd) via RF choke T₁, and a second end of theby-pass circuit is connected to transistor 446. The transmission line T₂454 and capacitor 452 are tuned to resonate at twice the frequencyoscillator, 2f_(o). With this arrangement, the tail noise and the supplynoise by-pass the tank 440 and the cross-coupled transistors 431, 432.

FIG. 12 illustrates a further embodiment of the invention, embodied inan integrated differential doubler. In this embodiment, circuit 462includes inductor 464, variable capacitor 466, and a pair ofcross-coupled transistors 470, 472. At one end of the oscillator, V_(dd)is connected to inductor 466 through inductor 474 and transistor 476,and a voltage reference 480 is applied to the gate of this transistor.The second end of the oscillator is connected to current source 482.This second end of the oscillator is also connected to V_(dd) viatransistor 484 and inductor 486, as shown in the Fig.

Noise by-pass circuit 490 is connected across inductor 464, capacitor466, and cross-coupled transistors 470, 472; and the tail noise and thesupply noise by-pass inductor 464, capacitor 466 and transistors 470,472. In this embodiment, noise by-pass circuit 490 includes oscillator492 and transmission line 494. One end of the by-pass circuit isconnected to oscillator circuit 462, above current source 482, and asecond end of the by-pass circuit is connected to the oscillatorcircuit, above inductor 464. This second end of the by-pass circuit isalso connected to the reference voltage 480 via capacitor 496.

With the architecture of FIG. 12, the double frequency amplitude isequalized and increased due to the supply tail coupling. A differentialdoubler with current re-use can be designed while reducing VCO noisesimultaneously. To do this, the by-pass 490 is tuned to twice theoscillation frequency for both applications.

FIG. 13 is a flow chart showing a design methodology 500 of anembodiment of this invention. At step 502, the LC VCC core is designed,biased, and connected to a voltage supply. The noise by-pass circuit isdesigned, at step 504, at approximately twice the oscillation frequencyof the VCO core. The by-pass circuit is, at step 506, introduced in theVCO, between the supply and tail nodes. At step 510, the by-pass circuitis tuned; and as represented at 512, the tuning is continued until thedesired performance, such as performance that minimizes phase noise, isreached.

FIG. 14 shows a circuit diagram 520 of an embodiment of this inventionand an illustration 522 of an implementation of that circuit in asemiconductor device 524. Embodiments of the invention can beimplemented using a modified inductor topology. Due to the differentialnature, t-line is unaffected by the inductor signals. Embodiments of theinvention can be implemented in a semiconductor device with negligiblearea overhead and no power overhead.

In an implementation of an embodiment of the invention, from theinductor center-tap, one transmission line connects to supply; andanother transmission line connects through a capacitor to the tail node.In an implementation, at least one transmission line goes around theinductor at a considerable distance to avoid signal coupling between thet-line and the inductor.

In embodiments of the invention, the transmission lines are implementedon top of the spiral inductor placed symmetric to the differentialinductor The differential signals on the inductor couple to thetransmission lines; however, the transmission lines are placedsymmetrically so as to perfectly cancel the ac-coupled signals from theinductor to the transmission line. This helps to achieve a low area, lowloss implementation of the t-line capacitor short. This implementationalso does not consume any dc-power.

FIG. 15 shows a block diagram of an exemplary design flow 600 used forexample, in semiconductor IC logic design, simulation, test, layout, andmanufacture. Design flow 600 includes processes, machines and/ormechanisms for processing design structures or devices to generatelogically or otherwise functionally equivalent representations of thedesign structures and/or devices described above. The design structuresprocessed and/or generated by design flow 600 may be encoded onmachine-readable transmission or storage media to include data and/orinstructions that when executed or otherwise processed on a dataprocessing system generate a logically, structurally, mechanically, orotherwise functionally equivalent representation of hardware components,circuits, devices, or systems. Machines include, but are not limited to,any machine used in an IC design process, such as designing,manufacturing, or simulating a circuit, component, device, or system.For example, machines may include: lithography machines, machines and/orequipment for generating masks (e.g. e-beam writers), computers orequipment for simulating design structures, any apparatus used in themanufacturing or test process, or any machines for programmingfunctionally equivalent representations of the design structures intoany medium (e.g. a machine for programming a programmable gate array).

Design flow 600 may vary depending on the type of representation beingdesigned. For example, a design flow for building an applicationspecific IC (ASIC) may differ from a design flow for designing astandard component or from a design flow for instantiating the designinto a programmable array, for example a programmable gate array (PGA)or a field programmable gate array (FPGA) offered by Altera® Inc. orXilinx® Inc.

FIG. 15 illustrates multiple such design structures including an inputdesign structure 620 that is preferably processed by a design process610. Design structure 620 may be a logical simulation design structuregenerated and processed by design process 610 to produce a logicallyequivalent functional representation of a hardware device. Designstructure 620 may also or alternatively comprise data and/or programinstructions that when processed by design process 610, generate afunctional representation of the physical structure of a hardwaredevice. Whether representing functional and/or structural designfeatures, design structure 620 may be generated using electroniccomputer-aided design (ECAD) such as implemented by a coredeveloper/designer. When encoded on a machine-readable datatransmission, gate array, or storage medium, design structure 620 may beaccessed and processed by one or more hardware and/or software moduleswithin design process 610 to simulate or otherwise functionallyrepresent an electronic component, circuit, electronic or logic module,apparatus, device, or system such as those described above. As such,design structure 620 may comprise files or other data structuresincluding human and/or machine-readable source code, compiledstructures, and computer-executable code structures that when processedby a design or simulation data processing system, functionally simulateor otherwise represent circuits or other levels of hardware logicdesign. Such data structures may include hardware-description language(HDL) design entities or other data structures conforming to and/orcompatible with lower-level HDL design languages such as Verilog andVHDL, and/or higher level design languages such as C or C++.

Design process 610 preferably employs and incorporates hardware and/orsoftware modules for synthesizing, translating, or otherwise processinga design/simulation functional equivalent of the components, circuits,devices, or logic structures described above to generate a netlist 680which may contain design structures such as design structure 620.Netlist 680 may comprise, for example, compiled or otherwise processeddata structures representing a list of wires, discrete components, logicgates, control circuits, I/O devices, models, etc. that describes theconnections to other elements and circuits in an integrated circuitdesign. Netlist 680 may be synthesized using an iterative process inwhich netlist 680 is resynthesized one or more times depending on designspecifications and parameters for the device. As with other designstructure types described herein, netlist 680 may be recorded on amachine-readable data storage medium or programmed into a programmablegate array. The medium may be a non-volatile storage medium such as amagnetic or optical disk drive, a programmable gate array, a compactflash, or other flash memory. Additionally, or in the alternative, themedium may be a system or cache memory, buffer space, or electrically oroptically conductive devices and materials on which data packets may betransmitted and intermediately stored via the Internet, or othernetworking suitable means.

Design process 610 may include hardware and software modules forprocessing a variety of input data structure types including netlist680. Such data structure types may reside, for example, within libraryelements 930 and include a set of commonly used elements, circuits, anddevices, including models, layouts, and symbolic representations, for agiven manufacturing technology (e.g., different technology nodes, 32 nm,45 nm, 90 nm, etc.). The data structure types may further include designspecifications 640, characterization data 950, verification data 960,design rules 970, and test data files 985 which may include input testpatterns, output test results, and other testing information. Designprocess 610 may further include, for example, standard mechanical designprocesses such as stress analysis, thermal analysis, mechanical eventsimulation, process simulation for operations such as casting, molding,and die press forming, etc. One of ordinary skill in the art ofmechanical design can appreciate the extent of possible mechanicaldesign tools and applications used in design process 610 withoutdeviating from the scope and spirit of the invention. Design process 610may also include modules for performing standard circuit designprocesses such as timing analysis, verification, design rule checking,place and route operations, etc.

Design process 610 employs and incorporates logic and physical designtools such as HDL compilers and simulation model build tools to processdesign structure 620 together with some or all of the depictedsupporting data structures along with any additional mechanical designor data (if applicable), to generate a second design structure 690.Design structure 690 resides on a storage medium or programmable gatearray in a data format used for the exchange of data of mechanicaldevices and structures (e.g. information stored in a IGES, DXF,Parasolid XT, JT, DRG, or any other suitable format for storing orrendering such mechanical design structures). Similar to designstructure 620, design structure 690 preferably comprises one or morefiles, data structures, or other computer-encoded data or instructionsthat reside on transmission or data storage media and that whenprocessed by an ECAD system generate a logically or otherwisefunctionally equivalent form of one or more of the embodiments of theinvention described above. In one embodiment, design structure 690 maycomprise a compiled, executable HDL simulation model that functionallysimulates the devices described above.

Design structure 690 may also employ a data format used for the exchangeof layout data of integrated circuits and/or symbolic data format (e.g.information stored in a GDSII (GDS2), GL1, OASIS, map files, or anyother suitable format for storing such design data structures). Designstructure 690 may comprise information such as, for example, symbolicdata, map files, test data files, design content files, manufacturingdata, layout parameters, wires, levels of metal, vias, shapes, data forrouting through the manufacturing line, and any other data required by amanufacturer or other designer/developer to produce a device orstructure as described above and shown in FIG. 1. Design structure 690may then proceed to a stage 695 where, for example, design structure690: proceeds to tape-out, is released to manufacturing, is released toa mask house, is sent to another design house, is sent back to thecustomer, etc.

The circuits as described above are part of the design for an integratedcircuit chip. The chip design is created in a graphical computerprogramming language, and stored in a computer storage medium (such as adisk, tape, physical hard drive, or virtual hard drive such as in astorage access network). If the designer does not fabricate chips or thephotolithographic masks used to fabricate chips, the designer transmitsthe resulting design by physical means (e.g., by providing a copy of thestorage medium storing the design) or electronically (e.g., through theInternet) to such entities, directly or indirectly. The stored design isthen converted into the appropriate format (e.g., GDSII) for thefabrication of photolithographic masks, which typically include multiplecopies of the chip design in question that are to be formed on a wafer.The photolithographic masks are utilized to define areas of the wafer(and/or the layers thereon) to be etched or otherwise processed.

The method as described above is used in the fabrication of integratedcircuit chips. The resulting integrated circuit chips can be distributedby the fabricator in raw wafer form (that is, as a single wafer that hasmultiple unpackaged chips), as a bare die, or in a packaged form. In thelatter case the chip is mounted in a single chip package (such as aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (such as a ceramiccarrier that has either or both surface interconnections or buriedinterconnections). In any case the chip is then integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either (a) an intermediate product, such as a motherboard, or(b) an end product. The end product can be any product that includesintegrated circuit chips, ranging from toys and other low-endapplications to advanced computer products having a display, a keyboardor other input device, and a central processor.

While various embodiments are described herein, it will be appreciatedfrom the specification that various combinations of elements, variationsor improvements therein may be made by those skilled in the art, and arewithin the scope of the invention. In addition, many modifications maybe made to adapt a particular situation or material to the teachings ofthe invention without departing from essential scope thereof. Therefore,it is intended that the invention not be limited to the particularembodiment disclosed as the best mode contemplated for carrying out thisinvention, but that the invention will include all embodiments fallingwithin the scope of the appended claims.

1. A design structure comprising machine readable instructions tangiblyembodied in a machine readable hardware medium for design,manufacturing, or testing a semiconductor device, the design structure,when executed in the machine, generating a representation of asemiconductor substrate including a voltage controlled oscillator (VCO),the generating comprising: generating a representation of an LC tankcircuit for generating an oscillator output signal at an oscillatorfrequency (f_(o)); generating a representation of an oscillator coreincluding first and second cross-coupled semiconductor devices connectedto the tank circuit to provide regenerative feedback to the tank circuitto help maintain the oscillator output stable; generating arepresentation of a supply node connected to the oscillator core forconnecting the VCO to a voltage source; generating a representation of atail node connected to the oscillator core for connecting the VCO to acurrent source; and generating a representation of a noise by-passcircuit connected to the supply node and to the tail node, in parallelwith the LC tank circuit and the oscillator core, and forming alow-impedance path at a frequency approximately twice the oscillatorfrequency to at least partially immunize the oscillator core fromexternal noise and to reduce noise contribution from the cross-coupledsemiconductor devices.
 2. The design structure according to claim 1,wherein the noise by-pass circuit comprises a series resonance tuned toresonate at approximately twice the oscillator frequency.
 3. The designstructure according to claim 2, wherein the noise by-pass circuitincludes a capacitor and an inductor located in series.
 4. The designstructure according to claim 2, wherein the noise by-pass circuitincludes a capacitor and a transmission line located in series.
 5. Thedesign structure according to claim 2, wherein the VCO further comprisesa frequency control to apply a variable signal to the by-pass circuit toadjust the frequency at which the noise by-pass circuit resonates.